Job description
Your role will involve the RTL architecture, design, implementation, and verification of cutting-edge SerDes PHY DSP blocks. You will also work alongside system architects to enhance designs for optimal performance, power efficiency, area, and latency considerations. Applicants should hold a BS, MS, or PhD in Electrical or Computer Engineering and possess a minimum of 15 years of experience in digital design. A solid command of System Verilog, RTL development, and high-speed SerDes architecture is essential.
