Job Summary
The position involves spearheading extensive verification strategies for tailored video codec ASICs by overseeing the HLS workflows transitioning from C/C++ to RTL. The role places a strong emphasis on ensuring functional accuracy by implementing a combined methodology that includes software testing, co-simulation, and conventional UVM testbenches.
Responsibilities
- Manage and lead HLS workflows from C/C++ to RTL for custom ASIC video codecs.
- Develop and execute comprehensive verification strategies to ensure functional correctness.
- Utilize a hybrid approach encompassing software testing and co-simulation along with UVM testbenches in verification processes.
Qualifications
- Bachelor’s degree in a relevant engineering discipline.
- A minimum of 8 years of experience in design verification.
- Expertise in SystemVerilog, UVM, and C/C++ programming languages.
- Experience with High-Level Synthesis (HLS) and knowledge in video compression is highly preferred.
