Job Summary
The engineer will be responsible for drafting microarchitecture specifications and designing SystemVerilog RTL specifically for TPU compute subsystems. This role involves close collaboration with design validation and physical design teams to achieve superior silicon implementation and ensure timing closure.
Responsibilities
- Create microarchitecture specifications for TPU compute subsystems.
- Develop SystemVerilog RTL to support design initiatives.
- Work alongside design validation and physical design teams to optimize silicon quality and timing parameters.
Qualifications
- Bachelor’s degree in a relevant engineering discipline.
- A minimum of 4 years of experience in digital design using SystemVerilog.
- Strong understanding of computer architecture, with practical experience in processor or accelerator design.
