You will plan and execute the verification of complex digital design blocks for TPU hardware using SystemVerilog and UVM. This involves identifying verification scenarios, writing coverage measures, and debugging tests in collaboration with design engineers. Candidates must have a bachelor’s degree in a relevant engineering field and at least 4 years of experience in design verification. Proficiency in SystemVerilog/Verilog is required, with a preference for advanced degrees and experience in silicon design verification.
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