Job Summary
This role involves strategizing and implementing the validation of intricate digital design components tailored for TPU hardware through the utilization of SystemVerilog and UVM methodologies.
Responsibilities
- Develop and execute rigorous verification plans for digital design blocks.
- Identify and define various verification scenarios.
- Create and analyze coverage metrics to ensure thorough testing.
- Collaborate closely with design engineers to troubleshoot and refine tests.
Qualifications
- Bachelor’s degree in a relevant engineering discipline.
- Minimum of 4 years of experience in design verification.
- Strong proficiency in SystemVerilog and Verilog.
- Preference for candidates with advanced degrees and experience in silicon design verification.
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