As a leader in technical engagements, you will be responsible for overseeing the electrical and structural soundness of multi-voltage ASICs while orchestrating low-power signoff processes. Your responsibilities include validating physical netlists, addressing post-layout issues, and enhancing power intent metrics to confirm readiness for tape-out. Applicants should possess a bachelor’s degree in a pertinent engineering discipline, along with a minimum of 8 years of experience in validating physical netlists or managing low-power signoff initiatives. Expertise in static low-power rule checking tools and the IEEE 1801 UPF framework is necessary.
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