Job Summary
The role of the engineer involves complete ownership and execution of full-chip physical verification tasks, which include Design Rule Checks (DRC), Layout Versus Schematic (LVS) checks, and Electrostatic Discharge (ESD) signoff. This position requires the individual to leverage industry-standard verification tools and to enhance physical verification workflows specifically for advanced node System on Chips (SoCs). Additionally, the engineer will be responsible for ensuring tapeout readiness in collaboration with various design teams.
Responsibilities
- Perform full-chip physical verification, including DRC, LVS, and ESD signoff.
- Utilize industry-standard tools for verification processes.
- Develop and improve physical verification flows for advanced node SoCs.
- Coordinate with design teams to ensure readiness for tapeout.
Qualifications
- A bachelor’s degree in electrical engineering, computer engineering, or computer science.
- At least 5 years of experience in ASIC design or physical design flow development.
SpaceX provides equal employment opportunities to all employees and applicants for employment and prohibits discrimination and harassment of any type without regard to race, color, religion, age, sex, national origin, disability status, genetics, protected veteran status, sexual orientation, gender identity or expression, or any other characteristic protected by federal, state or local laws.
