Job Summary
The Physical Design Engineer is responsible for leading RTL synthesis and floorplanning efforts aimed at maximizing performance, power efficiency, and area constraints for intricate ASIC/SoC designs. This role emphasizes collaboration with architecture and verification teams to facilitate design convergence and assist in achieving timing closure.
Responsibilities
- Drive RTL synthesis and floorplanning processes for complex ASIC and SoC designs.
- Optimize performance, power, and area metrics throughout the design lifecycle.
- Work collaboratively across various teams, including architecture and verification, to ensure effective design integration.
- Support timing closure activities to meet project deadlines and specifications.
Qualifications
- Bachelor’s or Master’s degree in Electrical or Computer Engineering.
- A minimum of 10 years of relevant industry experience in physical design.
- Deep understanding of RTL synthesis and floorplanning for advanced technology nodes.
- Strong skills in netlist optimization techniques.
