Sunnyvale, California, 94087

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Full Time
Onsite
$163000 - $236000/yr

Job Summary

The role involves defining and documenting the microarchitecture for digital designs associated with the TPU, while also working closely with cross-functional teams to meet objectives related to performance, power consumption, and area optimization. Additionally, the individual will spearhead the creation of internal design tools and assist in post-silicon validation processes.

Responsibilities

  • Define and document microarchitecture for TPU digital designs.
  • Collaborate with cross-functional teams to meet performance, power, and area targets.
  • Lead the development of tools for internal design processes.
  • Support validation efforts after silicon production.

Qualifications

  • A minimum of a bachelor’s degree in a relevant engineering discipline.
  • At least 8 years of experience in RTL design.
  • Master’s degree or PhD is preferred.
  • Extensive experience with power optimization techniques and design automation workflows is advantageous.

Google provides equal employment opportunities to all employees and applicants for employment and prohibits discrimination and harassment of any type without regard to race, color, religion, age, sex, national origin, disability status, genetics, protected veteran status, sexual orientation, gender identity or expression, or any other characteristic protected by federal, state or local laws.
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ASIC Design Engineer, Cloud TPU
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