You will develop and maintain UVM/SystemVerilog testbenches and verification plans for SoC blocks and subsystems. Additionally, you will debug simulation failures and contribute to regression infrastructure to ensure functional verification closure. Candidates must have a Bachelor’s, Master’s, or PhD in Electrical or Computer Engineering with at least 4 years of ASIC/SoC verification experience. Proficiency in UVM, SystemVerilog, and Python for automation is required, along with experience in coverage-driven verification.
Efficient Computer provides equal employment opportunities to all employees and applicants for employment and prohibits discrimination and harassment of any type without regard to race, color, religion, age, sex, national origin, disability status, genetics, protected veteran status, sexual orientation, gender identity or expression, or any other characteristic protected by federal, state or local laws.
