Job description
Your role will involve the RTL architecture, design, implementation, and verification of cutting-edge SerDes PHY DSP blocks. You will also work alongside system architects to enhance designs for optimal performance, power efficiency, area, and latency considerations. Applicants should hold a BS, MS, or PhD in Electrical or Computer Engineering and possess a minimum of 15 years of experience in digital design. A solid command of System Verilog, RTL development, and high-speed SerDes architecture is essential.
Credo provides equal employment opportunities to all employees and applicants for employment and prohibits discrimination and harassment of any type without regard to race, color, religion, age, sex, national origin, disability status, genetics, protected veteran status, sexual orientation, gender identity or expression, or any other characteristic protected by federal, state or local laws.
