Job Summary
The position involves overseeing the complete life cycle of functional verification for intricate ASICs, encompassing planning, developing tests, debugging, and ensuring coverage closure. The role also includes working in tandem with software and system validation teams to carry out test plans utilizing emulation platforms.
Responsibilities
- Manage the entire functional verification process for complex ASICs.
- Collaborate with teams to develop and execute comprehensive test plans.
- Engage in debugging activities to identify and resolve issues.
- Ensure coverage closure to achieve verification goals.
- Work alongside software and system validation teams on emulation platforms.
Qualifications
- Bachelor’s degree in Electrical Engineering.
- A minimum of 8 years of experience in verifying complex SoCs for server, storage, and networking applications.
- Strong expertise in System Verilog and UVM.
- Competency in scripting languages such as Python or Perl.
Astera Labs provides equal employment opportunities to all employees and applicants for employment and prohibits discrimination and harassment of any type without regard to race, color, religion, age, sex, national origin, disability status, genetics, protected veteran status, sexual orientation, gender identity or expression, or any other characteristic protected by federal, state or local laws.
