Job Summary
This role involves the design, development, verification, and optimization of RTL modules and digital circuits specifically tailored for ASIC and SoC platforms utilizing Verilog and SystemVerilog languages. The position requires a thorough understanding of various layers of VLSI design, focusing on enhancing both performance and efficiency.
Responsibilities
- Design and develop RTL modules and digital circuits for ASIC and SoC applications.
- Execute synthesis and simulation processes while analyzing power, performance, and area metrics.
- Debug design issues and assist in achieving timing closure.
- Collaborate effectively with different engineering teams to ensure project success.
Qualifications
- 2 to 8 years of experience in VLSI design or semiconductor engineering.
- Proficient in Verilog and SystemVerilog, with a solid background in RTL and digital logic design.
- Familiarity with ASIC and SoC methodologies, as well as tools for synthesis, simulation, and verification.
- Knowledge of timing analysis, CMOS fundamentals, and EDA tools such as Synopsys, Cadence, or Siemens EDA.
EdgeQ Technologies Private Limited provides equal employment opportunities to all employees and applicants for employment and prohibits discrimination and harassment of any type without regard to race, color, religion, age, sex, national origin, disability status, genetics, protected veteran status, sexual orientation, gender identity or expression, or any other characteristic protected by federal, state or local laws.
