Job Summary
The role involves designing and upholding UVM/SystemVerilog testbenches and verification strategies for integrated circuit blocks and subsystems. You will also be responsible for troubleshooting simulation issues and enhancing regression frameworks to achieve full functional verification compliance.
Responsibilities
- Develop and maintain UVM/SystemVerilog testbenches and verification plans.
- Debug simulation failures effectively.
- Contribute to the regression infrastructure to guarantee verification closure.
Qualifications
- Bachelor’s, Master’s, or PhD in Electrical or Computer Engineering.
- A minimum of 4 years of experience in ASIC/SoC verification.
- Strong proficiency in UVM, SystemVerilog, and Python aimed at automation.
- Familiarity with coverage-driven verification methodologies.
